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INTEGRATED CIRCUITS
74F569 4-bit bidirectional binary synchronous counter (3-State)
Product specification IC15 Data Handbook 1996 Jan 05
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
FEATURES
* 4-bit bidirectional counting - binary counter * Synchronous counting and loading * Look ahead carry capability for easy cascading * Preset capability for programmable operation * Master Reset (MR) overrides all other inputs * Synchronous Reset (SR) overrides counting and parallel loading * Clock Carry (CC) output to be used as a clock for flip-flops,
register and counters
PIN CONFIGURATION
U/D CP D0 D1 D2 D3 CEP MR SR 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC TC CC OE Q0 Q1 Q2 Q3 CET PE
* 3-State outputs for bus organized systems
DESCRIPTION
The 74F569 is a fully synchronous Up/Down binary counter. It features preset capabilities for programmable operation, carry look ahead for programmable operation, carry look ahead for easy cascading, and U/D input to control the direction of counting. For maximum flexibility there are both Synchronous and Master Reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by rising edge of the clock. A High signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.
GND 10
SF01072
TYPE 74F569
TYPICAL fMAX 115MHz
TYPICAL SUPPLY CURRENT (TOTAL) 40mA
ORDERING INFORMATION
ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V 10%, Tamb = 0C to +70C N74F569N N74F569D PKG. DWG. # SOT146-1 SOT163-1
20-pin plastic DIP 20-pin plastic SO
LOGIC SYMBOL
3 4 5 6
LOGIC SYMBOL (IEEE/IEC)
CTR DIV 10 17 EN10 M1[UP] M2[DOWN] 2 CC TC 18 19 12 7 9 Q0 Q1 Q2 Q3 11 C5/1,4,7,8+/2,4,7,8- Z6 G7 G8 5CT=0 M3[LOAD] M4[COUNT] 6,7,8,9 1,7(CT=15)G9 2,7(CT=0)G9 18 19
11 1 2 7 12 8 9 17
PE U/D CP CEP CET MR SR OE
D0
D1
D2
D3
1
VCC = Pin 20 GND = Pin 10
8 16 15 14 13
CT=0 16 15 14 13
SF01056
3 4 5 6 3,5D 10
SF01057
1996 Jan 05
2
853-0376 16193
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS D0 - D3 CEP CET CP PE U/D OE MR SR TC CC Parallel data inputs Count Enable parallel input (active Low) Count Enable Trickle input (active Low) Clock input (active rising edge) Parallel Enable input (active Low) Up/Down count control input Output Enable input Master Reset input (active Low) Synchronous Reset (active Low) Terminal count output (active Low) Clocked carry output (active Low) DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/2.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20A/0.6mA 20A/0.6mA 20A/1.2mA 20A/0.6mA 20A/1.2mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 20A/0.6mA 1.0mA/20mA 1.0mA/20mA 3.0mA/24mA
Q0 - Q3 Data outputs 150/40 NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20A in the High state and 0.6mA in the Low state.
FUNCTIONAL DESCRIPTION
The 74F569 counts in the modulo-16 binary sequence. From state 0 (LLLL) it will increment to 15 in the up mode; in the down mode it will decrement from 15 to 0. The clock inputs of all flip-flops are driven parallel through a clock buffer. All state changes (except due to Master Reset) occur synchronously with the Low-to-High transition of the Clock Pulse (CP) input. The circuit has five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Six control inputs-Master Reset (MR), Synchronous Reset (SR), Count Enable Trickle (CET), Parallel Enable (PE), Count Enable Parallel (CEP), and the Up/Down (U/D) input - determine the mode of operation, as shown in the Function Table. A Low signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs Low. A Low signal on SR overrides counting and parallel loading and allows the Q output to go Low on the next rising edge of CP. A Low signal on PE overrides counting and allows information on the parallel data (Dn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR, and PE High, CEP and CET permit counting when both are Low. Conversely, a High signal on either CEP and CET inhibits counting. The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally High and goes Low provided CET is Low, when the counter reaches zero in the down mode, or reaches maximum 15 in the up mode TC will then remain Low until a state change occurs by counting or presetting, or until U/D or CET is changed. To implement synchronous multistage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure 1 shows the connections for a simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry look ahead connections in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from Max to Min in the up mode, or Min to Max in the down mode, to start its final cycle. Since this takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, register or counters. For such applications, the Clocked Carry (CC) output is provided. The CC output is normally High. When CEP, CET, and TC are Low, the CC output will go Low, when the clock next goes Low and will stay Low until the clock goes High again; as shown in the CC Function Table. When the Output Enable (OE) is Low, the parallel data outputs Q0-Q3 are active and follow the flip-flop Q outputs. A High signal on OE forces Q0-Q3 to the High impedance state but does not prevent counting, loading or resetting. LOGIC EQUATIONS: Count Enable=CEPxCETxPE Up: TC=Q0xQ1xQ2xQ3x(Up)xCET Down: TC=Q0xQ1xQ2xQ3x(Down)xCET
1996 Jan 05
3
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
COUNT
CET
TC
CET
TC
CET
TC
CET
TC
CET
TC
CP
CP
TO ALL STAGES
SF01059
Figure 1. Multistage Counter with Ripple Carry
COUNT
CET
TC
CEP
CEP
CEP
CEP
CP CP TO ALL STAGES
LOW
CET
TC
CET
TC
CET
TC
CET
SF01061
Figure 2. Multistage Counter with Look-Ahead Carry
STATE DIAGRAM
0 1 2 3 4
CC FUNCTION TABLE
INPUTS SR L X PE X L X X X H CEP X X H X X L CET X X X H X L TC* X X X X H L CP X X X X X OUTPUT CC H H H H H
15
5
14
6
X X
13
7
X H * H L X = = = =
12
11
10
9
8
COUNT DOWN COUNT UP
SF01058
TC is generated internally High voltage level Low voltage level Don't care = Low Pulse
FUNCTION TABLE
INPUTS MR L h h h h h h H h L l X = = = = = = SR X l h h h H H PE X X l h h H H CEP X X X l l H X CET X X X l l X H U/D X X X h l X X CP X X Hold (do nothing) X High voltage level High voltage level one setup time prior to the Low-to-High clock transition Low voltage level Low voltage level one setup time prior to the Low-to-High clock transition Don't care Low-to-High clock transition OPERATING MODE Asynchronous reset Synchronous reset Parallel load Count Up (increment) Count Down (decrement)
1996 Jan 05
4
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
LOGIC DIAGRAM
OE 17 MR 8
D0
3
D
Q 16 Q0
CP Q RD
D1 4
D
Q
CP Q RD
15
Q1
D2
5
D
Q 14 RD Q2
CP Q
D3 SR 9
6
D
Q 13 Q3 RD
CP Q PE 11
7 CEP 12 CET CP U/D 2 1 19 TC
VCC = Pin 20 GND = Pin 10
18 CC
SF01062
1996 Jan 05
5
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER VCC VIN IIN VOUT IOUT Tamb Tstg Supply voltage Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state a lied out ut out ut Operating free-air temperature range Storage temperature TC, CC Qn RATING -0.5 to +7.0 -0.5 to +7.0 -30 to +5 -0.5 to +VCC 40 48 0 to +70 -65 to +150 UNIT V V mA V mA mA C C
RECOMMENDED OPERATING CONDITIONS
SYMBOL VCC VIH VIL IIK IOH IOL Tamb Supply voltage High-level input voltage Low-level input voltage Input clamp current High-level output current out ut Low-level out ut current output Operating free-air temperature range TC, CC Qn TC, CC Qn 0 PARAMETER LIMITS MIN 4.5 2.0 0.8 -18 -1 -3 20 24 70 NOM 5.0 MAX 5.5 V V V mA mA mA mA mA C UNIT
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.) LIMITS S O SYMBOL PARAMETER S CONDITIONSNO TAG OS TEST CO VCC = MIN, VIL = MAX, VIH = MIN, IOH = MAX VCC = MIN, VIL = MAX, VIH = MIN, IOL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V Others CET, PE VCC = MAX, VI = 0 5V MAX 0.5V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX VCC = MAX -60 38 43 40 10%VCC 5%VCC 10%VCC 5%VCC MIN 2.4 2.7 3.3 0.35 0.35 -0.73 0.50 0.50 -1.2 100 20 -0.6 -1.2 50 -50 -150 60 62 60 TYP
NO TAG
MAX
UNIT V V V V V A A mA mA A A mA mA mA mA
VOH VOL VIK II IIH IIL IOZH IOZL IOS ICC
High-level out ut voltage output Low-level out ut voltage output Input clamp voltage Input current at maximum input voltage High-level input current Low-level in ut current input Off-state output current, High-level voltage applied Off-state output current, High-level voltage applied Short-circuit output currentNO TAG ICCH Supply current (total) ICCL ICCZ
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1996 Jan 05 6
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
AC ELECTRICAL CHARACTERISTICS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITIONS MIN fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPLH tPHL tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Qn CC, TC Waveform 1 Waveform 2 Waveform 1 Waveform 2 Waveform 3 Waveform 4 Waveform 2 Waveform 2 Waveform 5 Waveform 4 Waveform 5 Waveform 3 Waveform 3 Waveform 10 Waveform 11 Waveform 10 Waveform 11 100 50 3.0 4.0 5.5 4.0 1.5 2.5 4.0 4.0 2.5 2.0 2.0 3.5 6.0 4.5 5.0 8.0 5.5 7.5 3.0 4.0 2.0 4.5 1.5 1.5 VCC = +5.V CL = 50pF, RL = 500 TYP 115 65 6.0 7.5 10.0 7.5 3.0 5.0 7.5 6.5 4.5 4.0 4.0 5.5 8.0 9.0 11.0 11.0 8.0 9.5 5.0 6.0 4.0 6.5 3.5 3.5 9.5 11.0 15.0 11.0 6.0 8.0 11.0 11.0 7.5 6.6 7.0 9.0 11.0 12.0 16.0 15.0 11.0 12.0 8.0 8.5 7.0 9.5 6.5 6.0 MAX Tamb = 0C to +70C VCC = +5.V 10% CL = 50pF, RL = 500 MIN 90 45 3.0 4.0 5.5 4.0 1.0 2.5 4.0 4.0 2.0 2.0 1.5 3.0 5.5 4.0 5.0 7.5 5.0 7.0 2.5 4.0 2.0 4.0 1.5 1.5 10.0 12.0 16.0 12.0 7.0 9.0 12.0 12.0 6.0 7.0 7.5 10.0 12.0 13.5 17.0 16.0 12.0 13.0 8.5 9.5 7.5 10.0 7.5 6.5 MAX MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
Propagation delay CP to Qn (PE, High or Low) Propagation delay CP to TC Propagation delay CET to TC Propagation delay U/D to TC Propagation delay CP to CC Propagation delay CEP, CET to CC Propagation delay MR to Qn Propagation delay U/D to CC Propagation delay MR to TC, CC Propagation delay SR to CC Propagation delay PE to CC Output Enable time to High or Low level OE to Qn Output Disable time to High or Low level OE to Qn
1996 Jan 05
7
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
AC SETUP REQUIREMENTS
LIMITS Tamb = +25C SYMBOL PARAMETER TEST CONDITIONS VCC = +5.0V CL = 50pF, RL = 500 MIN ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(H) tREC Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP Setup time, High or Low CEP or CET to CP Hold time, High or Low CEP or CET to CP Setup time, High or Low PE to CP Hold time, High or Low PE to CP Setup time, High or Low U/D to CP Hold time, High or Low U/D to CP Setup time, High or Low SR to CP Hold time, High or Low SR to CP CP Pulse width, High or Low MR Pulse width, Low Recovery time, MR to CP Waveform 6 Waveform 6 Waveform 7 Waveform 7 Waveform 6 Waveform 6 Waveform 8 Waveform 8 Waveform 9 Waveform 9 Waveform 1 Waveform 5 Waveform 5 4.0 4.0 2.0 2.0 5.0 5.0 0 0 8.0 8.0 0 0 10.0 8.0 0 0 8.0 8.0 0 0 7.0 5.0 4.5 6.0 TYP Tamb = 0C to +70C VCC = +5.0V 10% CL = 50pF, RL = 500 MIN 4.5 4.5 2.5 2.5 6.0 6.0 0 0 9.0 9.0 0 0 12.5 8.0 0 0 9.0 9.0 0 0 8.0 6.0 5.0 7.0 MAX ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
AC WAVEFORMS
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fMAX CP VM tW(H) tPLH VM Qn VM tW(L) tPHL VM CC tPHL VM tPLH VM VM TC CP, CEP, CET VM tPLH VM VM VM tPHL VM
SF01063
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
SF01064
Waveform 2. Propagation Delay, CP, CET, and CEP to CC and CP to TC
1996 Jan 05
8
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
CET, SR, PE VM tPHL TC, CC VM VM tPLH VM TC, CC
U/D
VM tPHL VM
VM tPLH VM
SF01065
SF01066
Waveform 3. Propagation Delays CET to TC and SR or PE to CC
Waveform 4. Propagation Delays U/D to TC and CC
tW(L) MR tREC Dn VM
DATA V STABLE M th
ts VM
CP tPHL
PE
VM
VM ts(L) th = 0
VM ts(H)
VM th = 0
Qn
VM CP
SF01067
VM
VM
Waveform 5. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time
SF01068
Waveform 6. Parallel Data and Parallel Enable Setup and Hold Times
CET VM CEP ts(L) th(L) ts(H) th(H) ts(L) th(L) ts(H) th(H) VM VM VM U/D VM VM VM VM
CP
VM
VM
CP
VM
VM
Qn
NO CHANGE
VM
COUNT
VM
NO CHANGE
Qn
COUNT UP
COUNT DOWN
SF01069
SF01070
Waveform 7. Count Enable Data Setup and Hold Times
Waveform 8. Up/Down Control Setup and Hold Times
SR
VM ts(H)
VM th(H)
VM ts(L)
VM th(L)
OE
VM tPZH
VM tPHZ VM 0V VOH -0.3V
Qn CP VM VM
SF01071
SF01084
Waveform 9. Synchronous Reset Setup and Hold Times
Waveform 10. 3-State Output Enable Time to High Level and Output Disable Time from High Level
1996 Jan 05
9
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
AC WAVEFORMS (Continued)
For all waveforms, VM = 1.5V The shaded areas indicate when the input is permitted to change for predictable output performance.
OE
VM tPZL
VM tPLZ VM VOL +0.3V
Qn
SF01083
Waveform 11. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
VCC 7.0V VIN PULSE GENERATOR RT D.U.T. VOUT RL NEGATIVE PULSE 90% VM 10% tTHL (tf ) CL RL tTLH (tr ) 90% POSITIVE PULSE 10% tTHL (tf ) AMP (V) 90% VM tw 10% 0V tw VM 10% tTLH (tr ) 0V AMP (V)
90%
Test Circuit for 3-State Outputs SWITCH POSITION TEST tPLZ tPZL All other SWITCH closed closed open
VM
Input Pulse Definition
DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate 1MHz tw 500ns tTLH 2.5ns tTHL 2.5ns
SF00777
1996 Jan 05
10
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
1996 Jan 05
11
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
1996 Jan 05
12
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
NOTES
1996 Jan 05
13
Philips Semiconductors
Product specification
4-bit bidirectional binary synchronous counter (3-State)
74F569
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05139

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